1. Field of the Invention
The present invention is directed to a layout structure with a fill element arranged within a substrate area.
2. Description of the Related Art
In order to provide for a uniform metal density distribution across a chip or locally within a chip or substrate area, a fill pattern comprising fill elements influencing the coupling characteristic and further supporting the silicon processing with an impact on the yield and performance may be generated.
Usually, fill elements are formed by conducting elements arranged e.g. in a vicinity of conducting lines. Unfortunately, a conductive fill pattern increases an interconnect (coupling) capacity which leads to an increased cross and noise coupling and therefore reduces the circuit performance and makes a timing sign-off difficult.
In order to achieve a uniform density, smaller fill shapes filling smaller empty areas or a reduced distance of the fill pattern with respect to the layout structure may be used. Unfortunately, the coupling capacity would increase even more in that case. Thus, although a higher density is achievable due to smaller fill shapes, the introduced parasitic capacity may have an impact on a signal's integrity.